Description
Universitat Politècnica de València (www.upv.es) is a public university with four campus sites, over 35,000 students and 2,600 faculty members and research staff. It consists of 44 Departments, most of them in engineering areas, and is the top University in Spain regarding patent production. Contributions to this project will come from the Parallel Architectures Group (GAP). GAP has a 26-year research expertise in different aspects of system architecture, especially on interconnection networks. Currently, the group is formed by twenty-nine researchers, eighteen of them being faculty members, and the remaining 11 members being students developing their PhD theses in the group. Participant members of the GAP group have lead research projects focused on FPGA and on-chip interconnects, providing also virtualization and partitioning support in embedded multicore systems. The members involved in RECIPE have developed a multicore architecture (from the basic processor, to the networks and memory hierarchy) developed in Verilog and ready for being used in the FPGA-based prototyping solution. Members of the team have recognized participation and contributions in top ranked conferences for Computer Architecture field and Parallel and Distributed Systems, being TPC member of ISCA, HPCA, Super Computing conference, as well as Associate Editor of IEEE journals like TC, CAL, and TPDS. The GAP group is member of the ETP4HPC platform, which defines the roadmap and European strategy for next generation HPC systems in Europe and defines the contents of the SRA.
Members of the team have designed and co-advised the development of an extension to the CUDA libraries, which enables unmodified CUDA-accelerated code to efficiently access virtualized GPUs located anywhere in the cluster. This extension significantly increases flexibility in the use of GPUs, enabling an application to use as many GPUs as required, increasing GPU utilization, increasing system throughput, ad reducing overall energy consumption to execute a given load. Role in the proposal UPV will focus on the deployment of hardware related support for RECIPE, paying special attention to the integration of the MANGO cluster (the team leads the MANGO project), the InfiniBand network, and the definition and implementation of the hardware abstraction layer. In particular, partitioning and reconfigurability support of the underlying hardware infrastructure for fault-tolerance and virtualization support will be provided. UPV will also work on low level runtime and firmware deployment for proper FPGA and IBA-related communication, leveraging the QoS InfiniBand mechanisms to provide real-time communication support through the resource manager. Memory coherence support will be also deployed in the HW accelerators.
Role in the project
UPV will focus on the deployment of hardware related support for RECIPE, paying special attention to the integration of the MANGO cluster (the team leads the MANGO project), the InfiniBand network, and the definition and implementation of the hardware abstraction layer. In particular, partitioning and reconfigurability support of the underlying hardware infrastructure for fault-tolerance and virtualization support will be provided. UPV will also work on low level runtime and firmware deployment for proper FPGA and IBA-related communication, leveraging the QoS InfiniBand mechanisms to provide real-time communication support through the resource manager. Memory coherence support will be also deployed in the HW accelerators.
Key personnel
Jose Flich got his PhD in 2001 in Computer Engineering. He is Full Professor at UPV where he leads the research activities related to NoCs. He has served in different conference program committees (ISCA, PACT, NOCS, ICPP, IPDPS, HiPC, CAC, ICPADS, ISCC), as program chair (INA-OCMC, CAC) and track co-chair (EUROPAR, SC). José Flich has collaborated with different Institutions (Ferrara, Catania, Jonkoping, USC) and companies (AMD, Intel, Sun). Current research activities focus on reconfiguration, routing, coherency protocols and congestion management within NoCs. He has co-invented different routing strategies, reconfiguration and congestion control mechanisms, some of them with high recognition (RECN and LBDR for on-chip networks). He is a member of the HIPEAC NoE. He has co-edited a book for the field of networks-on-chip. He was the Coordinator of the FP7 STREP NaNoC project and currently coordinates the FETHPC MANGO project.
Jose Duato is Professor in the Department of Computer Engineering (DISCA) at the Technical University of Valencia. His current research interests include interconnection networks, on-chip networks, and multicore and multiprocessor architectures. He published over 500 refereed papers. According to Google Scholar, his publications received more than 13,700 citations. He proposed a theory of deadlock-free adaptive routing that has been used in the design of the routing algorithms for the Cray T3E supercomputer, the on-chip router of the Alpha 21364 microprocessor, and the IBM BlueGene/L supercomputer. He also developed RECN, a scalable congestion management technique, and a very efficient routing algorithm for fat trees that has been incorporated into Sun Microsystem’s 3456-port InfiniBand Magnum switch. Prof. Duato led the Advanced Technology Group in the HyperTransport Consortium, and was the main contributor to the High Node Count HyperTransport Specification 1.0. He also led the development of rCUDA, which enables remote virtualized access to GP-GPU accelerators using a CUDA interface. Prof. Duato is the first author of the book “Interconnection Networks: An Engineering Approach”. He also served as a member of the editorial boards of IEEE Transactions on Parallel and Distributed Systems, IEEE Transactions on Computers, and IEEE Computer Architecture Letters. Prof. Duato was awarded with the National Research Prize in 2009 and the “Rey Jaime I” Prize in 2006.