The Barcelona Supercomputing Center (BSC) was established in 2005 and is the Spanish national supercomputing facility and a hosting member of the PRACE distributed supercomputing infrastructure. The Center houses MareNostrum, one of the most powerful supercomputers in Europe. The mission of BSC is to research, develop and manage information technologies in order to facilitate scientific progress.
BSC was a pioneer in combining HPC service provision, and R&D into both computer and computational science (life, earth and engineering sciences) under one roof. The centre fosters multidisciplinary scientific collaboration and innovation and currently has over 400 staff from 41 countries. In 2011, BSC was one of only eight Spanish research centres recognized by the national government as a “Severo Ochoa Centre of Excellence”.
BSC has collaborated with industry since its creation, and has participated in projects with companies such as ARM, Bull and Airbus as well as numerous SMEs. BSC also participates in various bilateral joint research centers with companies such as IBM, Microsoft, Intel, NVIDIA and Spanish oil company Repsol. The centre has been extremely
active in the EC Framework Programmes and has participated in over one hundred projects funded by it. BSC is a founding member of HiPEAC, the ETP4HPC and participates in the most relevant international roadmapping and discussion forums and has strong links to Latin America.
Education and Training is a priority for the centre and many of BSCs researchers are also university lecturers. BSC offers courses as a PRACE Advanced Training Centre, and through the Spanish national supercomputing network among others. The BSC Computer Sciences Department focuses on building upon currently available hardware and software
technologies and adapting these technologies to make efficient use of supercomputing infrastructures. The department proposes novel architectures for processors and memory hierarchy and develops programming models and innovative implementation approaches for these models as well as tools for performance analysis and prediction. The BSC is particularly active in the 7th Framework Programme and the H2020 Programme of the European Commission, participating in such high-profile computer sciences projects as: TERAFLUX, parMERASA, AXIOM, P-SOCRATES, DEEP, DEEP-ER, DEEP-EST Mont-Blanc 3, EuroEXA and being project coordinators in TEXT, VELOX, ENCORE, PROARTIS, PROXIMA, MONTBLANC (1 & 2).
Role in the project
BSC will contribute in many different aspects in RECIPE. BSC will led WP3 where is in charge of the timing analysis and the fault models development. BSC is also the responsible of the geophysical exploration use case that targets exploiting the FPGA acceleration capabilities enabled by RECIPE.
Carles Hernández is a senior PhD researcher in the CAOS group at BSC. In 2012 he worked as intern at the IP verification group at Intel Mobile Communications Munich. His area of expertise includes on-chip interconnects, processor design, FPGA prototyping, and reliability. He is currently co-advising 5 PhD students. Dr. Hernandez participates (has participated) in NaNoC, parMERASA, PROXIMA IP7 and VeTeSS ARTEMIS projects. In 2015 he was granted with a Young Researcher Grant by the Spanish Ministry to conduct research on high-performance and reliable processor design. He is currently leading the BSC hardware developments in the EFL project with the European Space Agency.
Dr Maurizio Hanzich leads the “HPC Software Engineering” group at the Computer Applications in Science and Engineering Department from the Barcelona Supercomputing Center, the Spanish National Supercomputing Institute. He is mainly focused in software research and development for the oil industry. He has a broad experience in the development of HPC software for the whole stack, from the hardware considerations to the application level. He’s been involved in European projects like PRACE, DEEP-ER, HPC4E and ASGARD as well as in industrial research contracts with companies like Repsol, for which he leads the developments. He’s the co-developer of the BSIT code (http://www.bsc.es/bsit/), an industrial seismic imaging package for oil & gas.
Jaume Abella is a senior PhD Researcher in the CAOS group at BSC and member of HIPEAC. He did a PhD on low power modelling and design and has a long-track record on modelling with probabilistic methods. He worked at the Intel Barcelona Research Center from 2005 to 2009 in the low-level design and modelling of circuits and microarchitectures for fault-tolerance and low power, and led the group on memory hierarchies. Jaume has authored 15 patents at Intel in the area of low-power and reliability. He joined the BSC in 2009 where he has been in charge of hardware designs for FP7 PROARTIS and PROXIMA, BSC certification activities in VeTeSS, and involved in two ESA projects. He has authored more than 80 papers in top conferences and journals in the area.